As the demand for application specific integrated circuits, often if referred to as ASICs, has continued to increase, so has the demand for design methodologies for forming these integrated circuits. The design methodologies rely greatly on the use of cells corresponding to various gates, flip/flops, etc., used within the ASIC. Thus, accurate models of the cells are required to provide accurate integrated circuit designs.
Extensive information regarding these cells is typically required to create accurate cells. This cell information is subsequently used by the following exemplary ASIC design tools including: simulators, timing verifiers, model dumpers, netlisters, synthesis tools, place and route tools, to design the integrated circuit. Such cell information typically includes timing information, capacitance information, power information and geometrical information. The timing information provides pin to pin delays, set-up and hold times, and minimum pulse width of a cell. The capacitance information provides the capacitance values of input/output pins of a cell. This information is used to compute delays using a delay model. With the advent of micron technologies, these delay models are increasingly sophisticated.
Typically there are two types of cells which are modeled. These cells include combinatorial cells and sequential cells. For combinatorial cells there is one type of input pin. Exemplary combinatorial cells include AND gates, OR gates, XOR gates and the like. Sequential cells have a plurality of pins such as data pins, clock pins, clear and preset pins. Exemplary sequential cells include flip/flops, latches and the like.
The pin to pin delay mentioned above is measured from the input pins to the output pins of the cell. The pin to pin delay is generally the time it takes for an input voltage change to cause the change of an output voltage. There can be several types of pin to pin delay depending on the edges of the output and/or the input. The types can be sorted by (rising output delay and falling output delay) or (rising input-rising output delay, rising input-falling output delay, falling input-rising output delay, and falling input-falling output delay). This delay information is extremely useful during the design process to assure proper timing throughout the cell.
One problem encountered in the utilization of conventional ASIC design tools and schemes has been the need for the user to generate stimuli to be applied to the subject cell to measure timing data within a simulator, such as SPICE.TM.. Such prior art devices and techniques involve this additional design step for ASIC formation. There exists a need to provide a ASIC design tool which automatically generates stimuli which is subsequently applied to a simulator to provide a timing characterization of the cell.